We are a small dynamic team working on leading edge networking IP looking for an experienced Digital Verification Manager with at least 7 years of solid ASIC digital design verification experience. The company is headquartered in San Jose, California with its primary design center in Pittsburgh, PA. The position we are hiring for is in Pittsburgh but the environment, pace, and expectations are very similar to a bay area startup.
The candidate show possess the following attributes:
- Bachelor or Masters Degree in Electrical and/or Computer Engineering
- 5+ years of experience that includes the following skills:
- SystemVerilog/UVM or other constrained random/testbench language/methodologies
- Ability to scope, plan, and track verification activities including test and coverage plans
- Good documentation and communication skills
- Detailed knowledge of networking protocols – specifically as 802.3 (Ethernet) and related standards
- Ability to manage and track multiple product regressions and succinctly and accurately report status
- Ability to architect a SystemVerilog/UVM test environment
- Unix/Linux, scripting (perl, tcl, python, shell)
- Advanced debug skills
- Self Starter
- Able to technically lead a small team
Interested in this role? Send us an email and let us know!