We are proud to offer a range of Ethernet IP, error correction IP, and security IP to our customer base in the core networking, semiconductor, and hyper-scale data center markets.
We do this by using design customization such as non-standard protocols, application driven special modes, sub-system integration and verification, and hard macros. Please see the sections below for more information.
CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and programmable to support “any rate on any channel” (800G/600G/400G/200G/100G/50G/25G/10G/1G). It uses a novel time-sliced architecture that affords maximum density for high port count applications while maintaining industry-leading latencies that are optimized for data center applications.
In addition to being compliant with the IEEE 802.3bs, IEEE 802.3-2012, 25G/50G Ethernet Consortium, IEEE 802.3by, and OIF Flex-E Standards, CoMira also offers non-standard and application-driven protocols and modes of operation that allow us to tailor each IP configuration to a customer’s specific needs. This, in turn, lets them better differentiate their own end products.
CoMira’s error correction and security IPs are available as seamless configuration add-on options that can be included with the UMAC IP.
- Programmable application-side FIFO sizes (or complete bypass ) on TX, RX or both for easy integration with application logic
- Packing and unpacking logic for application to internal data path matching
- Supports line rate with minimum IFG
- Memory-based statistics counter implementation for Area/gate savings
- IP core clock is independent of line rate and can be asynchronous to both the SerDes and application clocks
- Support for SerDes with parallel interfaces of multiple bit widths
- Virtual Lane Mapping (VLM) support of multiple SerDes
- Support for flow control using either standard or priority pause frames
- Jumbo frame support
- Per Frame IFG on transmit for frame pacing
- Per frame configurable preamble on transmit
- Per frame preamble extraction on receive
- Custom preamble length
- Frame time stamping on both transmit and receive
- Optional custom header insertion
- Per frame CRC control/CRC stomping
- Configurable statistics counters from 32 to 90+ per channel depending on application requirements
|Classification||Type||Product ID||BW (Gbps)||Max # of MAC Ch||Max # of PCS Ch||App width (bits)||Serdes Speed (Gbps)||RS(528,514)||RS(544,514)||RS(272,257+1)||FC(2112,2080)||BPAN||USXGMII||Fibre Ch||2-step TS||1-step TS||1G||MACSEC||Download|
|Multiple Channels||800||CMC800_F634||800||8||8||1024||106.25, 53.125||✓||✓||✓||✓||✓||✓||Download|
|400||CMC400_58AA||400||8||8||512||106.25, 53.125, 26.5625||✓||✓||✓||✓||Download|
|CMC400_3401||400||1||1||512||106.25, 53.125, 26.5625||✓||✓||✓||✓||Download|
|CMC400_519D||400||4||4||768||106.25, 53.125, 26.5625||✓||✓||✓||✓||Download|
|Single Channel||800||CSC800_871F||800||1||1||1024||106.25, 53.125, 26.5625||✓||✓||✓||✓||Download|
|400||CSC400_2189||400||1||1||512||106.25, 53.125, 26.5625||✓||✓||✓||✓||Download|
|100||CSC100_6764||100||1||1||128||106.25, 53.125, 26.5625||✓||✓||✓||Download|
Error Correction IP
As serial link speeds have increased, the reach achievable has become more and more limited by the lossy nature of the physical media which introduces the need for forward error correction (FEC) methods in the data-recovery functionality of Ethernet port logic. Starting at 10G line rates, Firecode was introduced into the 802.3 Ethernet Standard. The 802.3bj IEEE draft approved in June of 2014 introduced the Reed Solomon FEC algorithm for higher speed backplane and copper links.
CoMira provides a complete family of FEC cores for use in Ethernet (100G/50G/40G/25G/10G) and other applications. These cores may be purchased standalone, or as a configurable option of the CoMira UMAC IP. CoMira FEC IP is designed using a similar architecture employed in the UMAC to facilitate seamless integration of the former into the latter.
|FEC||Standard||Gain to 1e-12||Used In|
|802.3bj-2014 Clause 91||5.17db||100GBASE-KR4 50GBASE-R2 1
|802.3bj-2014 Clause 91||6.37db||100GBASE-KP4 2|
|802.3-2012 Clause 74||2.35db||50GBASE-R2 1
- Modes not specified as part of IEEE 802.3
- KP4 requires 3% overhead in SerDes
- Error statistics collected for each port and SerDes lane
- Error Indication / Error Correction can be bypassed.
- FEC operation can be bypassed to reduce latency
- SerDes independent backplane auto negotiation IP is also available upon request.
Media Access Control Security (MACSec) is an IEEE standards-based protocol for securing communication among the trusted components of an 802.1 LAN. MACSec provides protection against disruption of service, theft, and misuse of transmitted information (including network configuration information) by securing messages on the physical media.
CoMira’s MACSec IP implements the 802.1AE-2006 MACSec standard, as well as the 802.1AEbn-2011, 802.1AEbw-2013 amendments with additional support for the 802.1AEcg draft amendment. Using an inline time-division multiplexed cut-through architecture with a backpressure scheme similar to the UMAC, the multichannel CoMira MACSec IP is able to operate at the same core clock as the UMAC IP that is independent of the link speed and data flow.
- Up to four ports of concurrent traffic with an aggregate bandwidth of 100G are supported by one core (1x100G, 2x50G, 2x40G, 4x25G, 4x10G, 4x1G, 1x50G+2x25G)
- Line rate operation
- Flexible control/non-control port filtering
- Configurable number of Secure Channels (SCs) and Security Associations (SAs) per physical port
- Memory-based statistics counter implementation for area/gate savings
- Support for custom MACSec Ethertypes
- FIPS compliant GCM-AES-128, GCM-AES-256, GCM-AES-128-XPN, GCM-AES-256-XPN
- FCS regeneration on processed frames
- Configurable ability to select whether to strip SecTag, ICV, or both post-processing on Rx
- Support for a configurable number of VLAN tags preceding the SecTag in the MAC header