Tewksbury, MA – January 25, 2023 – Avery Design Systems, a leader in functional verification solutions, and high-speed connectivity IP innovator CoMira Solutions today announced a partnership aimed at enabling chiplet design using the UCIe (Universal Chiplet Interconnect Express) die-to-die interface standard. The combination of Avery’s verification IP (VIP) and functional verification platform and CoMira’s high-speed protocol stack controller technology currently under development will provide an efficient approach to for the design and verification of multi-die systems using the UCIe standard. Avery’s offering includes high-quality models and test suites that support pre-silicon verification of systems using UCIe.

UCIe was announced earlier this year as a mean to provide interoperability of chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. The focus of the initial specification (Version 1.0) covers the UCIe Adapter and PHY including die-to-die I/O physical layer, Die-to-Die protocols, and software stack which leverage the well-established PCI Express® (PCIe®) and Compute Express Link™ (CXL™) industry standards in addition to a protocol-agnostic raw transfer mode.

“CoMira is leveraging its extensive experience in high-speed connectivity IP to provide a reliable and easy-to-integrate UCIe protocol stack technology for multi-die systems. By supporting UCIe for connectivity within the chiplet architecture, and CXL and PCIe for external interfaces, we provide the necessary element for full chiplet connectivity,” said Qasim Shami, founder and CEO of CoMira Solutions. “Avery provides the ideal verification environment to allow pre-silicon validation for the entire chiplet system.”

“A key to success for any standard is a broad and robust ecosystem. Avery’s experience in enabling critical technology that is compliant with emerging standards accelerates timely, accurate design and verification to help meet the market requirements,” said Chris Browy, vice president sales and marketing at Avery.

Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its UCIe offering supports standalone UCIe die to die adapter and LogPHY verification along with integrated PCIe and CXL VIP to run over the UCIe stack. In addition to UCIe models it provides comprehensive protocol checkers, coverage, reference testbenches, and compliance test-suites utilizing a flexible and open architecture.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

About CoMira

CoMira helps the world’s most innovative semiconductor manufacturers make markets. The company’s high-performance Ethernet, Error Correction and Security IP solutions — along with a comprehensive services suite — enables silicon producers to get quickly into production, reduce die area and cost, and deliver differentiated offerings for a variety of applications. CoMira solutions are in some of the highest volume chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, the company has been a trusted partner for some of the biggest names in the business and specialized startups. To learn more about CoMira, visit www.comira-inc.com.

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Company Broadens Coverage in United States, Asia and Europe,
Joins Industry Leaders at CSIA – ICCAD 2022 Show

October 20, 2022 – CoMira Solutions, one of the world’s leading providers of IP for the semiconductor industry, today announced the opening of two new design and support offices for Asia in Pakistan, the expansion of its U.S.-based team in the company’s Pittsburgh R&D Center and additional support coverage in Europe. These moves extend CoMira’s ability to meet the needs of its growing customer base around the world.

“We’re excited to expand our global footprint,” said Qasim Shami, co-founder and CEO of CoMira. “We’re adding experts with a range of experience in semiconductor IP including architects and digital designers as well as specialists in advanced verification and ASIC implementation.”

CoMira’s IP is known for improving power efficiency and performance and reducing the semiconductor die area. The company’s technology appears in some of the world’s most advanced semiconductors for network, SmartNIC, DPU, artificial intelligence, and data center applications.

CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and programmable to support any rate on any channel up to 1.6TB. It uses a novel time-sliced architecture that affords maximum density for high port count applications. In addition to being compliant with the IEEE 802.3bs, IEEE 802.3-2012, 25G/50G Ethernet Consortium, IEEE 802.3by, and OIF Flex-E Standards, CoMira also offers non-standard and application-driven protocols and modes of operation that allow us to tailor each IP configuration to a customer’s specific needs.

CoMira representatives will showcase the company’s solutions at the CSIA – ICCAD 2022 Annual Conference & Guangzhou IC Industry Innovation and Development Summit in Guangzhou from November 9 to 10, 2022. Schedule a meeting by emailing CoMira at sales@comira-inc.com.

About CoMira
CoMira helps the world’s most innovative semiconductor manufacturers make markets. The company’s high-performance Ethernet, Error Correction and Security IP solutions — along with a comprehensive services suite — enables silicon producers to get quickly into production, reduce die area and cost, and deliver differentiated offerings for a variety of applications. CoMira solutions are in some of the highest volume chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, the company has been a trusted partner for some of the biggest names in the business and specialized startups. To learn more about CoMira, visit www.comira-inc.com.

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SAN JOSE, CALIFORNIA, UNITED STATES, March 29, 2022 /EINPresswire.com/ — eTopus Technology today announces the design-in availability of its 7/6nm multi-protocol SerDes IP optimized for PCIe gen 1 to 6 SoC & Chiplet clients. This new IP also supports Ethernet standards from 1G to 112G with support for long reach applications.

One of the key benefits of the new SerDes is its flexibility to support a wide range of channels from Short Reach (10dB) to Long Reach (up to 42dB) with low power of 6pj/bit.

“eTopus is a worldwide leader in high speed, low latency, low power connectivity IP which has shipped in millions of conventional ASICs” said Harry Chan, CEO of eTopus. “Now we are enabling SoC and Chiplet developers to go to market with lower risk and cost with silicon-proven IP supporting leading-edge PCIe and Ethernet connectivity.”

eTopus will demonstrate its 7/6nm SerDes IP running 64G PAM4 traffic with low BER at DesignCon 22 on April 5-7th in Santa Clara Convention Center at its Booth (#1255). The demonstration will showcase its BER performance over a 33dB insertion loss channel with connectors from Hirose Electric Co., Ltd.
eTopus has also chosen CoMira Solutions, Inc., the leading Ethernet MAC/PCS IP provider, as its solution partner for 800G/400G Ethernet solutions for integration with its 112G SerDes IP for next-generation ASIC and Chiplet applications.

“With 10s of millions of ICs shipped, CoMira IP is proven across a range of applications. We’re excited to now support eTopus with solutions for ASICs and Chiplets,” said Qasim Shami, Founder, and CEO of CoMira Solutions. “The Chiplet revolution is coming, and we see it as a major opportunity to increase performance while lowering client risk and time to market.”

Multiple options of the SerDes IP will be offered and introduced within the next few quarters.
HP SoC version:
– SerDes IP 1-64G/112G LR for PCIe Gen 5/6 and 800G/400G Ethernet operation on 7/6 nm, optimized for low latency and low power.

HP Chiplet version:
– SerDes IP & Controllers on Chiplet with Die-to-Die PHY
– Available for licensing as chiplets

LP SOC version:
– SERDES IP for PCI Gen 1-5 support & 56G LR SERDES for 400G support
– Optimized for today’s Gen 5 applications

About eTopus Technology Inc.
eTopus is the technology leader in high-performance, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect solutions. Our ultra-high-speed SerDes IP is adopted by global Tier-1 players to be used in networking, storage, 5G, and AI applications. eTopus is a VC-backed startup headquartered in Silicon Valley where our innovations and advanced architectures are developed. Our investors include SK Telecom, HK-X, corporate VCs, and cross-border funds. For more information, please visit www.etopus.com.

About CoMira Solutions, Inc.
CoMira helps innovative semiconductor manufacturers make markets. The company’s Ethernet, Error Correction and Security IP solutions — along with a complete services suite — enables companies to deliver chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, CoMira has been a trusted partner for some of the biggest names in technology and specialized startups. To learn more, visit www.comira-inc.com.