Senior Digital Verification Engineer

CoMira helps innovative semiconductor manufacturers make markets. The company’s Ethernet, Error Correction and Security IP solutions — along with a complete services suite — enables companies to deliver chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, CoMira has been a trusted partner for some of the biggest names in the business and specialized startups. To learn more, visit www.comira-inc.com.

This position is located at the CoMira Solutions design center in Pittsburgh, PA.

Working in this role, you will be a technical lead/expert contributing to our digital verification projects with our product development team. The role involves performing complex UVM/SystemVerilog based testing of our market leading High-Speed Ethernet, Error Coding, and Security IP than ultimately ends up in deep sub-micron semiconductor VLSI chips used in core network and high-end server equipment.

We are looking for a “hands on” active participant and technologist to provide expertise in Digital ASIC Design and Verification and to help continue to grow our exciting start-up company to the next level.

You will perform RTL design and verification using Verilog and SystemVerilog, object oriented tests using UVM, write documentation, develop verification environment, testbenches and verification components, verify design implementation, develop test benches and test cases for simulation platforms according to design/architecture specification, perform logic synthesis, and timing analysis.

Other verification duties include:

  • UVM/SystemVerilog Testbench architecture
  • UVM Agent development
  • Test Plan Development, Implementation
  • Functional Coverage Planning, Implementation, and Analysis
  • Design reviews
  • Scoping, planning, and tracking verification activities for several verification engineers on a project
  • Tracking multiple product regressions and succinctly and accurately report status

We are looking for an employee with more than 5 years of experience and knowledge of:

  • Networking protocols – specifically as 802.3 (Ethernet) and related standards
  • Security algorithms used in networking and adjacent domains
  • Forward Error Correction
  • Technical leadership
  • Verilog/SystemVerilog
  • Test benches, UVM, VIP
  • Perl/Python or other scripting
  • Unix/Linux scripting (perl, tcl, python, shell) with advanced debug skills
  • Strong Problem Solving/Analytic/Debug skills
  • FPGA implementation knowledge a plus
  • Tools: Cadence Incisive, Spyglass

Education Required: Bachelor or Masters Degree in Electrical and/or Computer Engineering

Interested? Apply on LinkedIn!

Verification Engineer

CoMira helps innovative semiconductor manufacturers make markets. The company’s Ethernet, Error Correction and Security IP solutions — along with a complete services suite — enables companies to deliver chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, CoMira has been a trusted partner for some of the biggest names in the business and specialized startups.

Working in this role, you will be a technical lead/expert contributing to our digital verification projects with our product development team.

We are looking for a “hands on” active participant and technologist to provide expertise in Digital ASIC Verification and to help continue to grow our exciting start-up company to the next level.

You will perform RTL verification using SystemVerilog and object oriented tests using UVM, write documentation, develop verification environments, testbenches and verification components, verify design implementations, and develop test benches and test cases for simulation platforms according to design/architecture specification.

Other verification duties include:

  • Architecting a SystemVerilog/UVM test environment
  • Creating a stimulus and test plan to verify a design per its functional specification and applicable standards
  • Designing and implementing UVM ComponentsUsing third-party VIP to verify components of the ASIC IP
  • Performing Code and Test Plan reviews
  • Planning for, implementing, and analyzing functional coverage
  • Scoping, planning, and tracking verification activities including test development, and test and coverage plan execution
  • Designing and tracking multiple product regressions while succinctly and accurately reporting status
  • Creating a UVM environment from scratch
  • Reviewing standards updates to ensure test plan remains in compliance
  • Debugging issues with the verification environment and tests
  • Recreating field issues using the verification environment

We are looking for an employee with more than 5 years of experience and knowledge of:

  • Networking protocols – specifically as 802.3 (Ethernet) and related standards
  • Security algorithms used in networking and adjacent domains
  • Forward Error Correction
  • Technical leadership
  • Verilog/SystemVerilog
  • Test benches, UVM,OVM,VIP
  • Creating UVM agents and environments from scratch
  • Perl/Python or other scripting
  • Unix/Linux scripting (perl, tcl, python, shell) with advanced debug skills
  • Advanced debugging skills
  • FPGA implementation knowledge a plus
  • Tools: Cadence Incisive, Genus, Spyglass

Education Required: Bachelor or Masters Degree in Electrical and/or Computer Engineering

This position is located at the CoMira Solutions Design Center in Pittsburgh, PA.

Interested? Apply on LinkedIn!

Digital Design Verification Engineer, Entry Level

This position is located at the CoMira’s design center in Pittsburgh, PA.

In this role, you will be contributing to our digital verification projects with our product development team. We are looking for a “hands on” active participant and technologist to help continue to grow our exciting start-up company. We are looking for full-time and interns!

You will be working with a small team of engineers. You will perform subsystem and full chip verification using Verilog by developing and running object oriented tests using UVM, developing verification environments, testbenches and verification components, test cases for according to design/architecture specification.

Duties include:

● ASIC digital design verification

● Scoping, planning, and tracking verification activities including test and coverage plans

● Tracking product regressions and succinctly and accurately reporting status

● Architecting a SystemVerilog/UVM test environment

We are looking for an employee with knowledge of:

● ASIC digital design verification

● Networking protocols – specifically as IEEE 802.3 and related standards

● Technical leadership

● RTL design and verification in System Verilog

● Testbench design with UVM

● Ethernet and other Network Protocols

● Python/Perl/Shell scripting.

● Advanced debugging skills

Education Required: Bachelor or Master’s Degree in Electrical and/or Computer Engineering

Interested in this role? Apply on LinkedIn!