CoMira Expands Global Support

Company Broadens Coverage in United States, Asia and Europe,
Joins Industry Leaders at CSIA – ICCAD 2022 Show

October 20, 2022 – CoMira Solutions, one of the world’s leading providers of IP for the semiconductor industry, today announced the opening of two new design and support offices for Asia in Pakistan, the expansion of its U.S.-based team in the company’s Pittsburgh R&D Center and additional support coverage in Europe. These moves extend CoMira’s ability to meet the needs of its growing customer base around the world.

“We’re excited to expand our global footprint,” said Qasim Shami, co-founder and CEO of CoMira. “We’re adding experts with a range of experience in semiconductor IP including architects and digital designers as well as specialists in advanced verification and ASIC implementation.”

CoMira’s IP is known for improving power efficiency and performance and reducing the semiconductor die area. The company’s technology appears in some of the world’s most advanced semiconductors for network, SmartNIC, DPU, artificial intelligence, and data center applications.

CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and programmable to support any rate on any channel up to 1.6TB. It uses a novel time-sliced architecture that affords maximum density for high port count applications. In addition to being compliant with the IEEE 802.3bs, IEEE 802.3-2012, 25G/50G Ethernet Consortium, IEEE 802.3by, and OIF Flex-E Standards, CoMira also offers non-standard and application-driven protocols and modes of operation that allow us to tailor each IP configuration to a customer’s specific needs.

CoMira representatives will showcase the company’s solutions at the CSIA – ICCAD 2022 Annual Conference & Guangzhou IC Industry Innovation and Development Summit in Guangzhou from November 9 to 10, 2022. Schedule a meeting by emailing CoMira at sales@comira-inc.com.

About CoMira
CoMira helps the world’s most innovative semiconductor manufacturers make markets. The company’s high-performance Ethernet, Error Correction and Security IP solutions — along with a comprehensive services suite — enables silicon producers to get quickly into production, reduce die area and cost, and deliver differentiated offerings for a variety of applications. CoMira solutions are in some of the highest volume chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, the company has been a trusted partner for some of the biggest names in the business and specialized startups. To learn more about CoMira, visit www.comira-inc.com.

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eTopus Partners with CoMira, Announces PCIe IP Gen 1-6 and 800G Support For 7/6nm With Support For SoC & Chiplet Clients

SAN JOSE, CALIFORNIA, UNITED STATES, March 29, 2022 /EINPresswire.com/ — eTopus Technology today announces the design-in availability of its 7/6nm multi-protocol SerDes IP optimized for PCIe gen 1 to 6 SoC & Chiplet clients. This new IP also supports Ethernet standards from 1G to 112G with support for long reach applications.

One of the key benefits of the new SerDes is its flexibility to support a wide range of channels from Short Reach (10dB) to Long Reach (up to 42dB) with low power of 6pj/bit.

“eTopus is a worldwide leader in high speed, low latency, low power connectivity IP which has shipped in millions of conventional ASICs” said Harry Chan, CEO of eTopus. “Now we are enabling SoC and Chiplet developers to go to market with lower risk and cost with silicon-proven IP supporting leading-edge PCIe and Ethernet connectivity.”

eTopus will demonstrate its 7/6nm SerDes IP running 64G PAM4 traffic with low BER at DesignCon 22 on April 5-7th in Santa Clara Convention Center at its Booth (#1255). The demonstration will showcase its BER performance over a 33dB insertion loss channel with connectors from Hirose Electric Co., Ltd.
eTopus has also chosen CoMira Solutions, Inc., the leading Ethernet MAC/PCS IP provider, as its solution partner for 800G/400G Ethernet solutions for integration with its 112G SerDes IP for next-generation ASIC and Chiplet applications.

“With 10s of millions of ICs shipped, CoMira IP is proven across a range of applications. We’re excited to now support eTopus with solutions for ASICs and Chiplets,” said Qasim Shami, Founder, and CEO of CoMira Solutions. “The Chiplet revolution is coming, and we see it as a major opportunity to increase performance while lowering client risk and time to market.”

Multiple options of the SerDes IP will be offered and introduced within the next few quarters.
HP SoC version:
– SerDes IP 1-64G/112G LR for PCIe Gen 5/6 and 800G/400G Ethernet operation on 7/6 nm, optimized for low latency and low power.

HP Chiplet version:
– SerDes IP & Controllers on Chiplet with Die-to-Die PHY
– Available for licensing as chiplets

LP SOC version:
– SERDES IP for PCI Gen 1-5 support & 56G LR SERDES for 400G support
– Optimized for today’s Gen 5 applications

About eTopus Technology Inc.
eTopus is the technology leader in high-performance, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect solutions. Our ultra-high-speed SerDes IP is adopted by global Tier-1 players to be used in networking, storage, 5G, and AI applications. eTopus is a VC-backed startup headquartered in Silicon Valley where our innovations and advanced architectures are developed. Our investors include SK Telecom, HK-X, corporate VCs, and cross-border funds. For more information, please visit www.etopus.com.

About CoMira Solutions, Inc.
CoMira helps innovative semiconductor manufacturers make markets. The company’s Ethernet, Error Correction and Security IP solutions — along with a complete services suite — enables companies to deliver chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, CoMira has been a trusted partner for some of the biggest names in technology and specialized startups. To learn more, visit www.comira-inc.com.

Senior Digital Verification Engineer

CoMira helps innovative semiconductor manufacturers make markets. The company’s Ethernet, Error Correction and Security IP solutions — along with a complete services suite — enables companies to deliver chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, CoMira has been a trusted partner for some of the biggest names in the business and specialized startups. To learn more, visit www.comira-inc.com.

This position is located at the CoMira Solutions design center in Pittsburgh, PA.

Working in this role, you will be a technical lead/expert contributing to our digital verification projects with our product development team. The role involves performing complex UVM/SystemVerilog based testing of our market leading High-Speed Ethernet, Error Coding, and Security IP than ultimately ends up in deep sub-micron semiconductor VLSI chips used in core network and high-end server equipment.

We are looking for a “hands on” active participant and technologist to provide expertise in Digital ASIC Design and Verification and to help continue to grow our exciting start-up company to the next level.

You will perform RTL design and verification using Verilog and SystemVerilog, object oriented tests using UVM, write documentation, develop verification environment, testbenches and verification components, verify design implementation, develop test benches and test cases for simulation platforms according to design/architecture specification, perform logic synthesis, and timing analysis.

Other verification duties include:

  • UVM/SystemVerilog Testbench architecture
  • UVM Agent development
  • Test Plan Development, Implementation
  • Functional Coverage Planning, Implementation, and Analysis
  • Design reviews
  • Scoping, planning, and tracking verification activities for several verification engineers on a project
  • Tracking multiple product regressions and succinctly and accurately report status

We are looking for an employee with more than 5 years of experience and knowledge of:

  • Networking protocols – specifically as 802.3 (Ethernet) and related standards
  • Security algorithms used in networking and adjacent domains
  • Forward Error Correction
  • Technical leadership
  • Verilog/SystemVerilog
  • Test benches, UVM, VIP
  • Perl/Python or other scripting
  • Unix/Linux scripting (perl, tcl, python, shell) with advanced debug skills
  • Strong Problem Solving/Analytic/Debug skills
  • FPGA implementation knowledge a plus
  • Tools: Cadence Incisive, Spyglass

Education Required: Bachelor or Masters Degree in Electrical and/or Computer Engineering

Interested? Send us an email!!

Verification Engineer

CoMira helps innovative semiconductor manufacturers make markets. The company’s Ethernet, Error Correction and Security IP solutions — along with a complete services suite — enables companies to deliver chips optimized for networking, artificial intelligence, machine learning, high-performance computing and servers. For more than 10 years, CoMira has been a trusted partner for some of the biggest names in the business and specialized startups.

Working in this role, you will be a technical lead/expert contributing to our digital verification projects with our product development team.

We are looking for a “hands on” active participant and technologist to provide expertise in Digital ASIC Verification and to help continue to grow our exciting start-up company to the next level.

You will perform RTL verification using SystemVerilog and object oriented tests using UVM, write documentation, develop verification environments, testbenches and verification components, verify design implementations, and develop test benches and test cases for simulation platforms according to design/architecture specification.

Other verification duties include:

  • Architecting a SystemVerilog/UVM test environment
  • Creating a stimulus and test plan to verify a design per its functional specification and applicable standards
  • Designing and implementing UVM ComponentsUsing third-party VIP to verify components of the ASIC IP
  • Performing Code and Test Plan reviews
  • Planning for, implementing, and analyzing functional coverage
  • Scoping, planning, and tracking verification activities including test development, and test and coverage plan execution
  • Designing and tracking multiple product regressions while succinctly and accurately reporting status
  • Creating a UVM environment from scratch
  • Reviewing standards updates to ensure test plan remains in compliance
  • Debugging issues with the verification environment and tests
  • Recreating field issues using the verification environment

We are looking for an employee with more than 5 years of experience and knowledge of:

  • Networking protocols – specifically as 802.3 (Ethernet) and related standards
  • Security algorithms used in networking and adjacent domains
  • Forward Error Correction
  • Technical leadership
  • Verilog/SystemVerilog
  • Test benches, UVM,OVM,VIP
  • Creating UVM agents and environments from scratch
  • Perl/Python or other scripting
  • Unix/Linux scripting (perl, tcl, python, shell) with advanced debug skills
  • Advanced debugging skills
  • FPGA implementation knowledge a plus
  • Tools: Cadence Incisive, Genus, Spyglass

Education Required: Bachelor or Masters Degree in Electrical and/or Computer Engineering

This position is located at the CoMira Solutions Design Center in Pittsburgh, PA.

Interested? Apply on LinkedIn!

Digital Design Verification Engineer, Entry Level

This position is located at the CoMira’s design center in Pittsburgh, PA.

In this role, you will be contributing to our digital verification projects with our product development team. We are looking for a “hands on” active participant and technologist to help continue to grow our exciting start-up company. We are looking for full-time and interns!

You will be working with a small team of engineers. You will perform subsystem and full chip verification using Verilog by developing and running object oriented tests using UVM, developing verification environments, testbenches and verification components, test cases for according to design/architecture specification.

Duties include:

● ASIC digital design verification

● Scoping, planning, and tracking verification activities including test and coverage plans

● Tracking product regressions and succinctly and accurately reporting status

● Architecting a SystemVerilog/UVM test environment

We are looking for an employee with knowledge of:

● ASIC digital design verification

● Networking protocols – specifically as IEEE 802.3 and related standards

● Technical leadership

● RTL design and verification in System Verilog

● Testbench design with UVM

● Ethernet and other Network Protocols

● Python/Perl/Shell scripting.

● Advanced debugging skills

Education Required: Bachelor or Master’s Degree in Electrical and/or Computer Engineering

Interested in this role? Apply on LinkedIn!