Digital Design Verification Engineer, Lead

Working In this role, you will be our technical lead/expert contributing to our digital verification projects with our product development team. We are looking for a “hands on” active participant and technologist to provide expert guidance to Digital ASIC Verification and to help continue to grow our exciting start-up company to the next level.

You will be leading a small team of engineers.  You will perform subsystem and full chip verification using Verilog, object oriented tests using UVM, develop verification environment, test benches and verification components, verify design implementation, develop test benches and test cases for simulation platform according to design/architecture specification.

Other duties include:

  • ASIC digital design verification
  • Scoping, planning, and tracking verification activities including test and coverage plans
  • Tracking multiple product regressions and succinctly and accurately report status
  • Architecting a SystemVerilog/UVM test environment
  • Creating UVM environment from scratch.

We are looking for an employee with more than 5 years of experience and knowledge of:

  • ASIC digital design verification
  • Networking protocols – specifically as 802.3 (Ethernet) and related standards
  • Technical leadership
  • System Verilog
  • Network Protocols
  • Ethernet 802.3 and other protocols
  • Creating UVMs from scratch
  • Perl/Python or other scripting
  • Unix/Linux scripting (perl, tcl, python, shell) with advanced debug skills
  • Advanced debugging skills
  • Test benches

Education Required: Bachelor or Masters Degree in Electrical and/or Computer Engineering

Interested in this role?  Send us an email and let us know!

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