Digital Design Verification Engineer, Entry Level

This position is located at the CoMIRA Solutions design center in Pittsburgh, PA.

In this role, you will be contributing to our digital verification projects with our product development team. We are looking for a “hands on” active participant and technologist to help continue to grow our exciting start-up company.

You will be working with a small team of engineers. You will perform subsystem and full chip verification using Verilog by developing and running object oriented tests using UVM, developing verification environments, testbenches and verification components, test cases for according to design/architecture specification.

Duties include:
ASIC digital design verification
Scoping, planning, and tracking verification activities including test and coverage plans
Tracking product regressions and succinctly and accurately reporting status
Architecting a SystemVerilog/UVM test environment

We are looking for an employee with knowledge of:

ASIC digital design verification
Networking protocols – specifically as IEEE 802.3 and related standards
Technical leadership
RTL design and verification in System Verilog
Testbench design with UVM
Ethernet and other Network Protocols
Python/Perl/Shell scripting.
Advanced debugging skills

Education Required: Bachelor or Master’s Degree in Electrical and/or Computer Engineering

Interested in this role? Send us an email and let us know!

Digital Design Verification Engineer, Lead

Working In this role, you will be our technical lead/expert contributing to our digital verification projects with our product development team. We are looking for a “hands on” active participant and technologist to provide expert guidance to Digital ASIC Verification and to help continue to grow our exciting start-up company to the next level.

You will be leading a small team of engineers.  You will perform subsystem and full chip verification using Verilog, object oriented tests using UVM, develop verification environment, test benches and verification components, verify design implementation, develop test benches and test cases for simulation platform according to design/architecture specification.

Other duties include:

  • ASIC digital design verification
  • Scoping, planning, and tracking verification activities including test and coverage plans
  • Tracking multiple product regressions and succinctly and accurately report status
  • Architecting a SystemVerilog/UVM test environment
  • Creating UVM environment from scratch.

We are looking for an employee with more than 5 years of experience and knowledge of:

  • ASIC digital design verification
  • Networking protocols – specifically as 802.3 (Ethernet) and related standards
  • Technical leadership
  • System Verilog
  • UVM,OVM,VIP
  • Network Protocols
  • Ethernet 802.3 and other protocols
  • Creating UVMs from scratch
  • Perl/Python or other scripting
  • Unix/Linux scripting (perl, tcl, python, shell) with advanced debug skills
  • Advanced debugging skills
  • Test benches

Education Required: Bachelor or Masters Degree in Electrical and/or Computer Engineering

Interested in this role?  Send us an email and let us know!

Verification Manager

We are a small dynamic team working on leading edge networking IP looking for an experienced Digital Verification Manager with at least 7 years of solid ASIC digital design verification experience. The company is headquartered in San Jose, California with its primary design center in Pittsburgh, PA. The position we are hiring for is in Pittsburgh but the environment, pace, and expectations are very similar to a bay area startup.


The candidate show possess the following attributes:

  1. Bachelor or Masters Degree in Electrical and/or Computer Engineering
  2. 5+ years of experience that includes the following skills:
  3. SystemVerilog/UVM or other constrained random/testbench language/methodologies
  4. Ability to scope, plan, and track verification activities including test and coverage plans
  5. Good documentation and communication skills
  6. Detailed knowledge of networking protocols – specifically as 802.3 (Ethernet) and related standards
  7. Ability to manage and track multiple product regressions and succinctly and accurately report status
  8. Ability to architect a SystemVerilog/UVM test environment
  9. Unix/Linux, scripting (perl, tcl, python, shell)
  10. Advanced debug skills
  11. Self Starter
  12. Able to technically lead a small team

Interested in this role? Send us an email and let us know!