Design Engineer

Job # 201

Duties:

– Conduct functional test and coverage plans, as well as environment and test development, debug, and result tracking for 100/40/10G and triple speed Ethernet IP and other digital design blocks, using electronic SystemVerilog/UVM constrained random verification methodology and class libraries, as well as Verilog language with simulators, etc.
 
– Participate in porting the above mentioned test cases into an integrated system environment, applying domain knowledge in SoC processor based systems.
 
– Participated in embedded C code test writing for such devices.
 
– Conduct test bench development for SoCs. Scripting in perl and tcl and shell.

Requirements: Bachelor’s in Electrical Engineering plus 2 years’experience

Interested in this role? Send us an email and let us know! Be sure to mention Job # 201!