Design Engineer


– Participate in the functional test and coverage plans, as well as environment and test development, debug, and

result tracking for 400G/200G/100/40/10G and triple-speed Ethernet IP, processor subsystems, and other digital

design blocks, applying knowledge of the Verilog language and experience with simulators such as

Modesim/Questa, VCS, or Incisive.

– Integrate peripheral sub-designs into an integrated system environment, applying domain knowledge in SoC

processor-based systems, including but not limited to MIPs processors, GPIO, uart, timer, USB and other common

processor peripherals.

– Conduct embedded C code test writing for such devices; develop test bench for SoCs, applying knowledge of

SystemVerilog/UVM constrained random verification methodology and class libraries as well as knowledge of the

Ethernet MAC and PCS standards, processor/computer architecture, and cache memory system principals.

– Perform digital logic synthesis and linting of digital designs described in RTL using Cadence Incisive and

Synopsys Spyglass, respectively.

– Conduct Ethernet line rate performance testing on a multi-speed, multi-channel Ethernet MAC-PCS DUT using

the Mentor Graphics Veloce Emulation Platform.

– Python scripting and generation of regression and synthesis results as well as UVM register models, and


Requirements: Bachelor’s in Electrical Engineering


Interested in this role?  Send us an email and let us know!